Complicated digital integrated circuits, such as FPGAs, microprocessors, application specific integrated circuits (ASICs), or the like (generally, chips), may have logic circuitry thereon arranged in groups, each group having a common power source. Each group of commonly powered logic circuits is typically referred to as a “power domain” or simply a “domain.” Each domain has its own one or more separate power source either on or off the chip.
Having separate power sources for each domain can reduce I2R loss, noise, and electromigration problems associated with on-chip power buses that carry a relatively large amount of current feeding many thousands of gates. In addition, it may be desirable to have different portions of the chip operate at different voltages to reduce the overall power consumption of the chip, e.g., core logic (programmable logic) may be operated at 1.2 volts or lower while peripheral logic (circuitry that couples the core logic to off-chip circuitry) may operate at 1.5 volts or higher. The core logic and peripheral logic may each have several domains.
Communication between logic circuits in different domains (or between different chips) can be problematic when logic voltage levels are sufficiently different between the domains/chips such that the logic gates in one domain/chip might not completely switch from one state to another state in response to logic signals received from another domain/chip. The resulting static (dc) current flow in the logic gates not completely switching states may lead to excess power consumption in the chip. This scenario is illustrated in FIG. 5.
FIG. 5 shows a conventional inverter 500 being driven by a logic gate 501. As illustrated, the logic gate 500 is in a domain powered from a power source VccH and inverter 501 is in a domain powered from a power source VccL (the domains being referred to herein as the VccH domain and the VccL domain, respectively, and the different domains may be on the same chip or different chips), resulting in the logic signal from gate 501 at node 502 ranging from approximately 0 volts (ground) to approximately VccL volts. Normally, the voltages of the VccL and VccH domains are substantially the same. Thus, if the logic signal on node 502 is approximately VccL volts, then the gate and source voltages of transistor 503 are substantially the same, turning off transistor 503 so that essentially no static current flows though it. As is sometimes the case, the voltage of VccL can be significantly less than the voltage of VccH. For example, if the voltage of the VccH domain exceeds the voltage of the VccL domain by the threshold voltage of transistor 503 and the logic signal at node 502 is VccL volts, then transistor 504 is fully conducting but transistor 503 is not completely turned-off. This results in a static current flow through transistors 503 and 504.
The static current flow problem, discussed above, may also manifest itself as a transient current flow problem. For example, it is possible that the voltage of the VccL domain will vary significantly as the logic gates in the domain switch state, possibly causing the domain voltage to temporarily droop sufficiently to induce static current flow in at least some of the logic gates in the VccH domain and/or other domains. Since there are possibly thousands of logic gates in a programmable device in each domain, the potential for large static current consumption (and corresponding high power dissipation) in one or more domains is large. Moreover, as transistors get smaller and the operating voltages of the transistors are commensurately reduced, domain voltage tolerances also become considerably tighter to avoid static current flow. The voltage tolerances may eventually become so tight that it becomes impractical to implement large chips with separate power domains or for one chip to communicate with another chip.
One remedy to the above-described problem is illustrated in FIG. 6. As shown, a gate 600 has therein an inverting buffer 601 followed by a NAND gate 602, both of which are powered from the VccH domain. Gate 600 is driven by two serial-coupled inverters 605, 606 powered from the VccL domain. The inverters 605, 606 provide complementary logic signals to nodes 607, 608, the inputs to the buffer 601. Buffer 601 consists of transistors 610-613 and an output logic signal from the output 615 of buffer 601 is applied to the NAND gate 602. NAND gate 602, responsive to logic signal input P, is needed to both invert logic signals passing through the buffer 601 as well as disable output signals from buffer 601 from reaching other logic circuits during power-up when logic signals to and from buffer 601 may be unknown or invalid. Transistors 612, 613 are cross-coupled so that, along with transistors 610, 611, the output logic signal on node 615 is stabilized as either a logic-high or logic-low state as determined by the complementary logic signals on nodes 607, 608. Because the logic signals on nodes 607, 608 drive only transistors 610, 611 and not transistors 612, 613, wide variations in voltage difference between VccL and VccH can be tolerated. However, this advantage comes at the cost. Among other complications, gate 600 has more circuitry (e.g., transistors 610 and 612, NAND gate 602, and inverter 606) when compared to the simple arrangement in FIG. 6. Moreover, complementary signals are needed to drive buffer 601, potentially doubling the number of connections between gates in different domains or between chips. Additionally, the propagation delay of logic signals through the inverters 605, 606, buffer 601, and gate 602 is longer than through the two simple inverters of FIG. 5, thereby limiting the speed of the chip implementing the circuit in FIG. 6.
It is therefore desirable to provide a high-speed, logic circuit that does not have significant static current drain over a wide range of input logic signal voltage levels. In addition, it is desirable that the logic circuit be able to perform complex logic functions so that it may be used in a wide variety of applications.